The present invention relates to a technology which is effective when applied to a technique for burying a plug in a silicon-based semiconductor substrate in a structure of a semiconductor device (or a semiconductor integrated circuit device) and a method of manufacturing the same.
In Japanese Unexamined Patent Publication No. 2007-053124 (Patent Document 1), disclosed is a technology for an integrated circuit including a Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOSFET) in which a silicon-based buried plug of poly-silicon or the like is formed in a silicon-based mono-crystalline semiconductor substrate.
In Japanese Unexamined Patent Publication No. 2004-103715 (Patent Document 2), disclosed is a technology for an integrated circuit in which, to reduce the ON resistance of a bipolar transistor, a silicon-based buried plug is formed in a silicon-based mono-crystalline semiconductor substrate.
In Japanese Unexamined Patent Publication No. 2003-158178 (Patent Document 3) or US Patent Publication No. 2003-0094669 (Patent Document 4), disclosed is a technology which uses, as a conductive plug, a silicon-based insulating buried isolation region present in an isolation region for isolating a plurality of bipolar transistors.
In Japanese Unexamined Patent Publication No. 2006-319282 (Patent Document 5), as a technique for cleaning the surfaces of trenches formed in a silicon-based mono-crystalline semiconductor substrate, a technique is disclosed which cleans the surfaces of the trenches using a diluted fluoric acid solution or the like, and then cleans the surfaces of the trenches by wet cleaning using an acidic solution as the final step of cleaning except for a pure water rinsing step.